Hideki Takase
Kyoto University / JST PRESTO
Audience: Intermediate, Advanced
Topic: Elixir

Cockatrice: A Hardware Design Environment with Elixir

Can you imagine that your Elixir code will be executed as a hardware circuit on an FPGA?

The FPGA (Field-Programmable Gate Array) is an integrated circuit designed to be configured after manufacturing as many times as needed. The internal architecture of FPGA is the systolic array, which consists of the logic blocks, the connection blocks, and the interconnects. One of the advantages of FPGA is that it can realize parallel processing to contribute to energy efficiency.

This talk will introduce the Cockatrice, a novel hardware design environment that treats the Elixir code as an HW design language. We found that the Elixir Zen style (the parallel programming style of Elixir using Flow, Enum, and the pipeline operator) has a strong affinity with the FPGA architecture. Therefore, we implement the Cockatrice to synthesize the Elixir Zen-styled code as the parallel circuit automatically. Our work would contribute to performance enhancement and energy savings of embedded/IoT systems.


Hideki Takase is an Assistant Professor at Kyoto University, and also a PRESTO researcher at Japan Science and Technology Agency. His research interest includes runtime platforms and system-level design methodologies for embedded/real-time/IoT computing. He belongs to some tech communities, such as fukuoka.ex, ROS Japan User Group, IoT ALGYAN, hls-friends, TOPPERS project, and so on. He loves the Nerves technology in the Elixir ecosystem.